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Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B430F512GQ64 /QSPI0 /ROUTEPEN

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Interpret as ROUTEPEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SCLKPEN)SCLKPEN 0 (CS0PEN)CS0PEN 0 (CS1PEN)CS1PEN 0 (DQ0PEN)DQ0PEN 0 (DQ1PEN)DQ1PEN 0 (DQ2PEN)DQ2PEN 0 (DQ3PEN)DQ3PEN 0 (DQ4PEN)DQ4PEN 0 (DQ5PEN)DQ5PEN 0 (DQ6PEN)DQ6PEN 0 (DQ7PEN)DQ7PEN 0 (DQSPEN)DQSPEN 0 (SCLKINPEN)SCLKINPEN 0 (RST0PEN)RST0PEN 0 (RST1PEN)RST1PEN

Description

I/O Routing Pin Enable Register

Fields

SCLKPEN

SCLK Pin Enable
CS0PEN

CS0 Pin Enable
CS1PEN

CS1 Pin Enable
DQ0PEN

DQ0 Pin Enable
DQ1PEN

DQ1 Pin Enable
DQ2PEN

DQ2 Pin Enable
DQ3PEN

DQ3 Pin Enable
DQ4PEN

DQ4 Pin Enable
DQ5PEN

DQ5 Pin Enable
DQ6PEN

DQ6 Pin Enable
DQ7PEN

DQ7 Pin Enable
DQSPEN

DQS Pin Enable
SCLKINPEN

SCLKIN Pin Enable
RST0PEN

RST0 Pin Enable
RST1PEN

RST1 Pin Enable

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data